Semiconductor device

ABSTRACT

A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a first recess, a second recess, a passivation layer, and an etch mask layer. The group III-V barrier layer includes a thinner portion, a first thicker portion and a second thicker portion in the active region, the thinner portion surrounds the first thicker portion, and the second thicker portion surrounds the thinner portion. The first recess is disposed in the group III-V barrier layer in the active region. The second recess is disposed in the group III-V barrier layer in the isolation region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser.No. 17/321,534, filed on May 17, 2021, which is a continuationapplication of U.S. application Ser. No. 16/655,252, filed on Oct. 17,2019. The contents of these applications are incorporated herein byreference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present disclosure relates to the field of high electron mobilitytransistors, and more particularly to an enhancement mode high electronmobility transistor.

2. Description of the Prior Art

In semiconductor technology, group III-V semiconductor compounds may beused to form various integrated circuit (IC) devices, such as high powerfield-effect transistors (FETs), high frequency transistors, or highelectron mobility transistors (HEMTs). A HEMT is a field effecttransistor having a two dimensional electron gas (2-DEG) layer close toa junction between two materials with different band gaps (i.e., aheterojunction). The 2-DEG layer is used as the transistor channelinstead of a doped region, as is generally the case for metal oxidesemiconductor field effect transistors (MOSFETs). Compared with MOSFETs,HEMTs have a number of attractive properties such as high electronmobility and the ability to transmit signals at high frequencies. In theprocesses for fabricating the conventional HEMTs, however, multiplephotolithographic and etching processes are required to define thesource/drain regions of the HEMTs and the isolation region between twoadjacent HEMTs, which increases the complexity of the overall process.In addition, the isolation region between two adjacent HEMTs is oftenmore recessed than the regions surrounding the isolation region, whichalso affects the flatness of the interconnection in the isolationregion. Therefore, there is a need to improve the above drawbacks.

SUMMARY OF THE INVENTION

In view of this, it is necessary to provide an improved high electronmobility transistor without the drawbacks of the conventional highelectron mobility transistors.

According to one embodiment of the present disclosure, a semiconductordevice is disclosed and includes an enhancement mode high electronmobility transistor (HEMT) with an active region and an isolationregion. The HEMT includes a substrate, a group III-V body layer, a groupIII-V barrier layer, a first recess, a second recess, a passivationlayer, and an etch mask layer. The group III-V body layer is disposed onthe substrate. The group III-V barrier layer is disposed on the groupIII-V body layer in the active region and the isolation region, whereinthe group III-V barrier layer includes a thinner portion, a firstthicker portion and a second thicker portion in the active region, thethinner portion surrounds the first thicker portion, and the secondthicker portion surrounds the thinner portion. The first recess isdisposed in the group III-V barrier layer in the active region. Thesecond recess is disposed in the group III-V barrier layer in theisolation region. The etch mask layer is disposed between thepassivation layer and the group III-V barrier layer in the activeregion, wherein the etch mask layer is spaced apart from bottoms of thefirst recess and the second recess.

According to another embodiment of the present disclosure, asemiconductor device is disclosed and includes an active region and anisolation region. The semiconductor device includes a substrate, a groupIII-V body layer, and a group III-V barrier layer. The group III-V bodylayer is disposed on the substrate. The group III-V barrier layer isdisposed on the group III-V body layer in the active region, wherein thegroup III-V barrier layer includes a thinner portion, a first thickerportion, and a second thicker portion in the active region. The firstthicker portion and the second thicker portion are respectively disposedat two sides of the thinner portion, the thinner portion surrounds thefirst thicker portion, and the second thicker portion surrounds thethinner portion.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a top plan view of a semiconductor device in accordance withone embodiment of the present disclosure.

FIG. 2 is a cross-sectional view of a semiconductor device in accordancewith one embodiment of the present disclosure.

FIG. 3 is a cross-sectional view of a semiconductor device having a bodylayer, a barrier layer, and an etch mask layer disposed on a substratein accordance with one embodiment of the present disclosure.

FIG. 4 is a cross-sectional view of a semiconductor device after an etchmask layer is patterned in accordance with one embodiment of the presentdisclosure.

FIG. 5 is a cross-sectional view of a semiconductor device after a groupIII-V barrier layer is patterned in accordance with one embodiment ofthe present disclosure.

FIG. 6 is a cross-sectional view of a semiconductor device after apassivation layer is deposited in accordance with one embodiment of thepresent disclosure.

FIG. 7 is a cross-sectional view of a semiconductor device after contacthole are formed in a passivation layer in accordance with one embodimentof the present disclosure.

FIG. 8 is a cross-sectional view of a semiconductor device after aconductive structure is formed in a contact hole in accordance with oneembodiment of the present disclosure.

FIG. 9 is a flow chart of a method of fabricating a semiconductor devicein accordance with one embodiment of the present disclosure.

FIG. 10 is a top plan view of an enhancement mode high electron mobilitytransistor in accordance with one embodiment of the present disclosure.

FIG. 11 is a top plan view of an enhancement mode high electron mobilitytransistor in accordance with another embodiment of the presentdisclosure.

DETAILED DESCRIPTION

The present disclosure may be understood by reference to the followingdetailed description, taken in conjunction with the drawings asdescribed below. It is noted that, for purposes of illustrative clarityand being easily understood by the readers, various drawings of thisdisclosure show a portion of the device, and certain elements in variousdrawings may not be drawn to scale. In addition, the number anddimension of each device shown in drawings are only illustrative and arenot intended to limit the scope of the present disclosure.

Certain terms are used throughout the following description to refer toparticular components. One of ordinary skill in the art would understandthat electronic equipment manufacturers may use different technicalterms to describe the same component. The present disclosure does notintend to distinguish between the components that differ only in namebut not function. In the following description and claims, the terms“include”, “comprise”, and “have” are used in an open-ended fashion andthus should be interpreted as the meaning of “include, but not limitedto”.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. The terms“comprises,” “comprising,” “includes” and/or “including” are inclusiveand therefore specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

It is understood that, although the terms first, second, third, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms may be onlyused to distinguish one element, component, region, layer and/or sectionfrom another region, layer and/or section. Terms such as “first,”“second,” and other numerical terms when used herein do not imply asequence or order unless clearly indicated by the context. Thus, a firstelement, component, region, layer and/or section discussed below couldbe termed a second element, component, region, layer and/or sectionwithout departing from the teachings of the embodiments.

When an element or layer is referred to as being “coupled to” or“connected to” another element or layer, it may be directly coupled orconnected to the other element or layer, or intervening elements orlayers may be presented. In contrast, when an element is referred to asbeing “directly coupled to” or “directly connected to” another elementor layer, there are no intervening elements or layers presented.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forththe broad scope of the disclosure are approximations, the numericalvalues set forth in the specific examples are reported as precisely aspossible. Any numerical value, however, inherently contains certainerrors necessarily resulting from the standard deviation found in therespective testing measurements. Also, as used herein, the term “about”generally means in 10%, 5%, 1%, or 0.5% of a given value or range.Alternatively, the term “about” means in an acceptable standard error ofthe mean when considered by one of ordinary skill in the art. Other thanin the operating/working examples, or unless otherwise expresslyspecified, all of the numerical ranges, amounts, values and percentagessuch as those for quantities of materials, durations of times,temperatures, operating conditions, ratios of amounts, and the likesthereof disclosed herein should be understood as modified in allinstances by the term “about.” Accordingly, unless indicated to thecontrary, the numerical parameters set forth in the present disclosureand attached claims are approximations that may vary as desired. At thevery least, each numerical parameter should at least be construed inlight of the number of reported significant digits and by applyingordinary rounding techniques. Ranges may be expressed herein as from oneendpoint to another endpoint or between two endpoints. All rangesdisclosed herein are inclusive of the endpoints, unless specifiedotherwise.

It should be noted that the technical features in different embodimentsdescribed in the following may be replaced, recombined, or mixed withone another to constitute another embodiment without departing from thespirit of the present disclosure.

The present disclosure is directed to a group III-V high electronmobility transistor (HEMT) and method for fabricating the same. III-VHEMTs on silicon substrates are used as power switching transistors forvoltage converter applications. Compared to silicon power transistors,III-V HEMTs feature low on-state resistances and low switching lossesdue to wide bandgap properties. In the present disclosure, a “groupIII-V semiconductor” refers to a compound semiconductor that includes atleast one group III element and at least one group V element, wheregroup III element may be boron (B), aluminum (Al), gallium (Ga) orindium (In), and group V element may be nitrogen (N), phosphorous (P),arsenic (As), or antimony (Sb). Furthermore, the group III-Vsemiconductor may refer to, but not limited to, gallium nitride (GaN),indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide(GaAs), aluminum gallium nitride (AlGaN), indium aluminum galliumnitride (InAIGaN), indium gallium nitride (InGaN) and the like. In asimilar manner, a “μl-nitride semiconductor” refers to a compoundsemiconductor that includes nitrogen and at least one group III element,such as, but not limited to, GaN, aluminum nitride (AlN), indium nitride(InN), AlGaN, InGaN, InAIGaN and the like.

FIG. 1 is a top plan view of a semiconductor device in accordance withone embodiment of the present disclosure. Referring to FIG. 1 , asemiconductor device 10 may include several high electron mobilitytransistors, such as a first high electron mobility transistor (HEMT)100-1 and a second high electron mobility transistor 100-2. Each of thehigh electron mobility transistors may have the same configuration, andthus each of the high electron mobility transistors may be regarded as arepeating unit in the semiconductor device 10. Taking the first highelectron mobility transistor 100-1 as an example, it may include anactive region 102A and an isolation region 102B. Source/drain regions104 and 106 and gate region 108 may be disposed in active region 102Aand thus may be used to transmit current and/or turn on or off thecurrent. The isolation region 102B is disposed around the active region102A and may be used to avoid unnecessary electrical coupling betweenthe adjacent two active regions 102A. In accordance with one embodimentof the present disclosure, the source/drain region 104 may be disposedat a center region of the active region 102A, such that the gate region108 may surround the source/drain region 104 and the source/drain region106 may surround the gate region 108. In addition, in order to reducethe contact resistance, low-resistance conductive electrodes, such as asource/drain electrode 110, a gate electrode 114, and a source/drainelectrode 112 may be disposed on the surfaces of the source/drain region104, the gate region 108, and the source/drain region 106, respectively.In accordance with one embodiment of the present disclosure, the gateelectrode 114 may fully surround the source/drain region 104. However,the gate electrode 114 may be disposed on only one side or both sides ofthe source/drain region 104 according to another embodiment, but notlimited thereto.

FIG. 2 is a cross-sectional view of a semiconductor device taken along aline A-A′ of FIG. 1 in accordance with one embodiment of the presentdisclosure. Referring to FIG. 1 and FIG. 2 , the semiconductor device 10includes at least a substrate 120, a group III-V body layer 124, a groupIII-V barrier layer 126, and a first recess 128A. The group III-V bodylayer 124 is disposed on the substrate 120, and the group III-V barrierlayer 126 is disposed on the group III-V body layer 124 in the activeregion 102A and the isolation region 102B. The first recess 128A may beformed in the group III-V barrier layer 126 in the active region 102A.Specifically, the group III-V barrier layer 126 may be continuouslydistributed in the active region 102A or further continuouslydistributed in the active region 102A and the isolation region 102B.Portions of the III-V barrier layer 126 may have a thickness T1 greaterthan the thickness T2 of other portions of the III-V barrier layer 126.For example, the thickness T1 may be between 30-80 nm and the thicknessT2 may be between 2-10 nm. By providing the group III-V barrier layer126 with different thicknesses in predetermined regions, a 2-dimensionalelectron gas (2-DEG) may or may not be generated in the correspondingregions in the III-V body layer 124 under the group III-V barrier layer126. In accordance with one embodiment of the present disclosure, theposition of the group III-V barrier layer 126 with the thickness T1 maycorrespond to the positions of the source/drain regions 104 and 106.Thus, a 2-DEG region 140 may be generated in the corresponding III-Vbody layer 124 under the group III-V barrier layer 126 with thethickness T1. In contrast, the position of the group III-V barrier layer126 with the thickness T2 may correspond to the position of the gateregion 108 or the isolation region 102B. Thus, a 2-DEG cutoff region 142may be generated in the corresponding III-V body layer 124 under thegroup III-V barrier layer 126 with the thickness T2. Since theresistance of the 2-DEG cutoff region 142 is much larger than theresistance of the 2-DEG region 140, the 2-DEG cutoff region 142 may beregarded as an electrical isolation region. According to the presentdisclosure, by providing the group III-V barrier layer 126 withdifferent thicknesses, the 2-DEG may be formed only in specific regions,such as only in the source/drain regions 104 and 106.

In addition, a passivation layer 132 may be further disposed on thegroup III-V barrier layer 126 in order to reduce surface defects on thesurface of the group III-V barrier layer 126. In accordance with oneembodiment of the present disclosure, the passivation layer 132 may indirect contact the bottom of the first recess 128A, or even fill up thefirst recess 128A. Since the depth of the first recess 128A is notgreater than 150 nm, the passivation layer 132 in the active region 102Amay have a flat top surface. In this way, the interconnections formed onthe passivation layer 132 during the following processes may becontinuously distributed on the passivation layer 132 without breakage.

The group III-V body layer 124 may include one or more layers of groupIII-V semiconductor composed of GaN, AlGaN, InGaN, or InAIGaN, but isnot limited thereto. In addition, the group III-V body layer 124 mayalso be one or more layers of doped group III-V semiconductor, such asp-type III-V semiconductor. For the p-type group III-V semiconductor,the dopants of which may be C, Fe, Mg or Zn, but is not limited thereto.The group III-V barrier layer 126 may include one or more layers ofgroup III-V semiconductor with the composition different from that ofthe group III-V semiconductor of the group III-V body layer 124. Forexample, the group III-V barrier layer 126 may include AlN,Al_(y)Ga_((1-y))N(0<y<1), or a combination thereof. In accordance withone embodiment, the group III-V body layer 124 may be an undoped GaNlayer, and the group III-V barrier layer 126 may be an inherent n-typeAlGaN layer. Since there is a bandgap discontinuity between the groupIII-V body layer 124 and the group III-V barrier layer 126, by stackingthe group III-V body layer 124 and the group III-V barrier layer 126 oneach other (and vice versa), a thin layer with high electron mobility,also called a two-dimensional electron gas, may be accumulated near theheterojunction between the group III-V body layer 124 and the groupIII-V barrier layer 126 due to the piezoelectric effect. The compositionof the passivation layer 132 may include aluminum nitride, aluminumoxide or silicon nitride, but not limited thereto.

In accordance with one embodiment, an additional buffer layer 122 may befurther disposed between the substrate 120 and the group III-V bodylayer 124. The purpose of the buffer layer 122 may be to reduce stressor lattice mismatch between the substrate 120 and the group III-V bodylayer 124.

In accordance with one embodiment of the present disclosure, an etchmask layer 130 may be further disposed between the group III-V barrierlayer 126 and the passivation layer 132. During an etching process ofpatterning the III-V barrier layer 126, the etch mask layer 130 maycover portions of the group III-V barrier layer 126 in order to definethe position of the first recess 128A. The composition of the etch masklayer 130 may include silicon nitride or silicon oxide. In accordancewith one embodiment of the present disclosure, the etch mask layer 130may further be used to define the location of another recess (alsocalled a second recess 128B). Specifically, the first recess 128A andthe second recess 128B are disposed in the group III-V barrier layer 126and are in the active region 102A and the isolation region 102B,respectively. The etch mask layer 130 may be regarded as being spacedapart from the first recess 128A and the second recess 128B, or beingspaced apart from the bottoms of the first recess 128A and the secondrecess 128B. In addition, portions of the group III-V barrier layer 126are exposed from the bottoms of the first recess 128A and the secondrecess 128B. Thus, the passivation layer 132 may be filled into not onlythe first recess 128A in the active region 102A but also the secondrecess 128B in the isolation region 102B.

In accordance with one embodiment of the present disclosure, thesource/drain electrodes 110 and 112 and the gate electrode 114 are alldisposed in the active region 102A, and the bottom of the gate electrode114 is disposed in the first recess 128A. The source/drain electrodes110 and 112 and the gate electrode 114 may be in direct contact with thegroup III-V barrier layer 126 such that the source/drain electrodes 110and 112 and the gate electrode 114 are all electrically coupled to thecorresponding group III-V barrier layer 126. By properly biasing thesource/drain electrodes 110 and 112, current may flow into or out of thesource/drain regions 104 and 106. In addition, by properly biasing thegate electrode 114, the conductance of the carrier channel may beadjusted so that current may be able to flow between the source/drainregions 104 and 106.

The source/drain electrodes 110 and 112 and the gate electrode 114 maybe single-layered or multi-layered structures, respectively, and thecompositions thereof may include Al, Cu, W, Au, Pt, Ti, polysilicon, orother low resistance semiconductor, metal or alloy, but not limitedthereto.

In order to enable one of ordinary skill in the art to implement thepresent disclosure, a method of fabricating a semiconductor device ofthe present disclosure is further described below.

FIG. 3 is a schematic cross-sectional view of a semiconductor devicewhere a body layer, a barrier layer, an etch mask layer are disposed ona substrate in accordance with one embodiment of the present disclosure.Referring to FIG. 3 , the substrate 120 may be divided into the activeregions 102A and the isolation region 102B disposed between the activeregions 102A. The buffer layer 122, the group III-V body layer 124, thegroup III-V barrier layer 125, and the etch mask layer may be stacked onthe substrate 120 in sequence. The substrate 120 may be a bulk siliconsubstrate, a silicon carbide (SiC) substrate, a sapphire substrate, asilicon on insulator (SOI) substrate or a germanium on insulator (GOI)substrate, but not limited thereto. The stacked layers on the substrate120 may be formed through any suitable growth processes, such asmolecular-beam epitaxy (MBE), metal-organic chemical vapor deposition(MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition(ALD) or other suitable growth processes. The buffer layer 122 mayinclude a plurality of sub-semiconductor layers (i.e., multiple layers)and the overall resistance of the buffer layer 122 may be higher thanthe resistance of other layers on the substrate 120. Specifically, theratio of some elements, such as metal element, of the buffer layer 122may be changed gradually along a direction from the substrate 120 to thegroup III-V body layer 124. For example, for a case where the substrate120 and the group III-V body layer 124 are a silicon substrate and a GaNlayer, respectively, the buffer layer 122 may be graded aluminum galliumnitride (Al_(x)Ga_((1-x))N) where there is a continuous or stepwisedecrease in the x ratio from 0.9 to 0.15 along the direction from thesubstrate 120 to the group III-V body layer 124. In another case, thebuffer layer 122 may have a superlattice structure. Since there is abandgap discontinuity between the group III-V body layer 124 and thegroup III-V barrier layer 126, the 2-DEG region 140 may be generatednear the heterojunction between the group III-V body layer 124 and thegroup III-V barrier layer 125.

FIG. 4 is a cross-sectional view of a semiconductor device after an etchmask layer is patterned in accordance with one embodiment of the presentdisclosure. After the process shown in FIG. 3 , the etch mask layer 127disposed on the group III-V barrier layer 125 may be further patternedby appropriate lithographic and etching processes so as to form apatterned etch mask layer 130. Since portions of the group III-V barrierlayer 125 is not covered by the etch mask layer 130, at least portionsof the group III-V barrier layer 125 not covered by the etch mask layer130 may be etched in the subsequent etching process to thereby formrecesses in the group III-V barrier layer 125.

FIG. 5 is a cross-sectional view of a semiconductor device after a groupIII-V barrier layer is patterned in accordance with one embodiment ofthe present disclosure. After the process shown in FIG. 4 , a suitableetching process may be carried out by using the etch mask layer 130 asan etch mask. A patterned III-V barrier layer 126 may be formed duringthe etching process in which the group III-V barrier layer 125 notcovered by the etch mask layer 130 is etched. Thus, the first recess128A and the second recess 128B may be formed in the active region 102Aand the isolation region 102B concurrently, and the group III-V barrierlayer 126 is exposed from the bottoms of the first recess 128A and thesecond recess 128B. In accordance with one embodiment of the presentdisclosure, the thickness T2 of the group III-V barrier layer 126 underthe first recess 128A and the second recess 128B may be between 2-10 nm.According to another embodiment of the present disclosure, the groupIII-V barrier layer 126 under the first recess 128A and the secondrecess 128B may be etched away completely such that the group III-V bodylayer 124 is exposed from the bottoms of the first recess 128A and thesecond recess 128B. By forming the first recess 128A and the secondrecess 128B in the active region 102A and the isolation region 102B,respectively, the 2-DEG cutoff region 142 may be generated under thefirst recess 128A and the second recess 128B.

FIG. 6 is a cross-sectional view of a semiconductor device after apassivation layer is deposited in accordance with one embodiment of thepresent disclosure. After the process shown in FIG. 5 , the passivationlayer 132 may then be deposited comprehensively such that thepassivation layer 132 may not only cover the group III-V barrier layer126 and the etch mask layer 130 but also fill the first recess 128A andthe second recess 128B. The composition of the passivation layer 132includes, but not limited to, aluminum nitride, aluminum oxide orsilicon nitride, which may be used to eliminate or reduce surfacedefects on the surface of the group III-V barrier layer 126. Therefore,the electron mobility in the 2-DEG region 140 may be increased.

FIG. 7 is a cross-sectional view of a semiconductor device after contactholes are formed in a passivation layer in accordance with oneembodiment of the present disclosure. After the process shown in FIG. 6, appropriate photolithographic and etching processes may then becarried out to form contact holes 134 in the passivation layer 132. Inaccordance with one embodiment of the present disclosure, the contactholes 134 are formed only in the active region 102A and are not in theisolation region 102B. In addition, some of the contact holes 134 maypenetrate not only the passivation layer 132 but also the etch masklayer 130. Thus, portions of the group III-V barrier layer 126 may beexposed from the bottoms of the contact holes 134.

FIG. 8 is a cross-sectional view of a semiconductor device afterconductive structures are formed in contact holes in accordance with oneembodiment of the present disclosure. After the process shown in FIG. 7, suitable deposition and etching processes may be carried out to formconductive structures filling the contact holes 134. The conductivestructures may be source/drain electrodes 110 and 112 and gate electrode114. The composition of the conductive structures may include titanium,aluminum or doped polysilicon, but not limited thereto. The source/drainelectrodes 110 and the source/drain electrodes 112 may be electricallycoupled to the source/drain region 104 and the source/drain regions 106in the active region 102A, respectively, while the gate electrode 114may be electrically coupled to the group III-V barrier layer 126 at thebottom of the first recess 128A. In accordance with one embodiment ofthe present disclosure, the source/drain electrodes 110, thesource/drain electrodes 112, and the gate electrodes 114 are disposedonly in the active region 102A and are not in the isolation region 102B.In other words, the source/drain electrodes 110, the source/drainelectrodes 112, and the gate electrodes 114 may be spaced apart from thesecond recess 128B.

Still referring to FIG. 8 , suitable deposition and etching processesmay then be carried out to form several conductive interconnections 150on the surface of the passivation layer 132. The interconnections 150may be electrically coupled to the underlying source/drain electrodes110, source/drain electrodes 112, and gate electrodes 114. Since thedepths of the first recess 128A and the first recess 128B (the depth isthe sum of the thickness of the etch mask layer 130 and the thickness T1of the group III-V barrier layer 126) is not more than 150 nm, thepassivation layer 132 in the active region 102A and the isolation region102B may have a flat top surface such that the interconnections 150formed over the passivation layer 132 may be continuously distributedwithout breakage. In addition, another interlayer dielectric or etchstop layer may be disposed between the passivation layer 132 and theinterconnections 150, but not limited thereto.

According to the present disclosure, the semiconductor device 10 mayinclude at least two enhancement mode high electron mobility transistorsrespectively disposed in the active regions 102A, and the two adjacentenhancement mode high electron mobility transistors may have a commonisolation region 102B. The group III-V barrier layer 126 is a continuouslayer disposed in the active region 102A and the isolation region 102Band is disposed between the two adjacent enhancement mode high electronmobility transistors. Since the first recess 128A and the second recess128B respectively in the active region 102A and the isolation region102B may be concurrently formed through the same photolithographic andetching process, the processes for fabricating the semiconductor devicemay be simplified. In other words, in accordance with one embodiment ofthe present invention, the active region 102A and the isolation region102B may be defined by using the same reticle without using anotherreticle to define a mesa region. In addition, the depth of the isolationregion 102B between the two adjacent high electron mobility transistorsmay not be too deep, such as less than 150 nm, so that theinterconnections 150 in the isolation region 102B may have a betterflatness.

FIG. 9 is a flow chart of a method of fabricating a semiconductor devicein accordance with one embodiment of the present disclosure. Inaccordance with one embodiment of the present disclosure, a method 200of fabricating a high electron mobility transistor may include: step202: provide a semiconductor substrate having a group III-V body layerand a group III-V barrier layer thereon; step 204: form a first recessand a second recess in the group III-V barrier layer, and the firstrecess and the second recess are in an active region and an isolationregion respectively; step 206: deposit a passivation layer on thebottoms of the first recess and the second recess, and portions of thegroup III-V barrier layer are at the bottoms of the first recess and thesecond recess.

FIG. 10 is a top plan view of an enhancement mode high electron mobilitytransistor in accordance with one embodiment of the present disclosure.The semiconductor device 10 shown in FIG. 10 is substantially similar tothe semiconductor device 10 shown in FIG. 1 , but the difference betweenthe two is mainly in the design layout of the source/drain regions 104and 106 and the gate region 108. Specifically, the semiconductor device10 shown in FIG. 10 includes at least one high electron mobilitytransistor 100-1, and the source/drain region 104 is disposed in themiddle region. The layout of the semiconductor device 10 may be acircular layout so that both the gate region 108 and the source/drainregions 106 may surround the source/drain region 104 in turn. Thus,current may flow between the source/drain region 104 and thesource/drain region 106 by biasing the gate region 108. In addition, theconductive electrodes, such as the source/drain electrodes 110 and 112and the gate electrodes 114, may be disposed on the surfaces of thesource/drain regions 104 and 106 and the gate region 108, respectively.The area of the source/drain electrode 110 may be smaller than the areaof the source/drain region 104, and the source/drain electrode 110 maybe electrically coupled to the interconnection 150-1. The source/drainelectrode 112 may have an area that is less than the area of thesource/drain region 106 and may be electrically coupled to theinterconnection 150-2. The gate electrode 114 may surround thesource/drain region 104, and the gate electrode 114 may have an areasmaller than the area of the gate region 108 and may be electricallycoupled to the interconnection 150-3.

FIG. 11 is a top plan view of an enhancement mode high electron mobilitytransistor in accordance with one embodiment of the present disclosure.The semiconductor device 10 shown in FIG. 11 is substantially similar tothe semiconductor device 10 shown in FIG. 10 , but the differencebetween the two is mainly in the design layout of the source/drainregions 104 and 106 and the gate region 108. Specifically, thesource/drain region 104 of the semiconductor device 10 shown in FIG. 11is disposed in the center region. The layout of the semiconductor device10 may be a rectangular layout so that both the gate region 108 andsource/drain regions 106 may surround the source/drain region 104 inturn. Besides, the gate region 108 and source/drain regions 106 may alsohave rectangular layouts. The semiconductor device 10 shown in FIG. 11may also have the conductive electrodes and interconnections, and theconfiguration thereof is substantially similar to the configurationshown in FIG. 10 , the description of which is omitted for the sake ofbrevity.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A semiconductor device, comprising: anenhancement mode high electron mobility transistor (HEMT) comprising anactive region and an isolation region, wherein the enhancement mode HEMTcomprises: a substrate; a group III-V body layer, disposed on thesubstrate; a group III-V barrier layer, disposed on the group III-V bodylayer in the active region and the isolation region; a first recess,disposed in the group III-V barrier layer in the active region; a secondrecess, disposed in the group III-V barrier layer in the isolationregion; a passivation layer, disposed in the first recess and the secondrecess; and an etch mask layer, disposed between the passivation layerand the group III-V barrier layer in the active region, wherein the etchmask layer is spaced apart from bottoms of the first recess and thesecond recess, wherein the group III-V barrier layer comprises a thinnerportion, a first thicker portion and a second thicker portion in theactive region, the thinner portion surrounds the first thicker portion,and the second thicker portion surrounds the thinner portion.
 2. Thesemiconductor device of claim 1, wherein the semiconductor devicefurther comprises: at least two source/drain electrodes disposed on thefirst thicker portion and the second thicker portion, respectively; anda gate electrode disposed on the thinner portion.
 3. The semiconductordevice of claim 1, wherein the first recess is disposed on the thinnerportion.
 4. The semiconductor device of claim 1, wherein the firstrecess is not greater than 150 nm.
 5. The semiconductor device of claim1, wherein a depth of the first recess and a depth of the second recessare the same.
 6. The semiconductor device of claim 1, wherein the firstrecess and the second recess are separated by the second thickerportion.
 7. The semiconductor device of claim 1, wherein a thickness ofthe first thicker portion is 30 to 80 nm, and a thickness of the secondthicker portion is 30 to 80 nm.
 8. The semiconductor device of claim 7,wherein the thickness of the first thicker portion and the thickness ofthe second thicker portion are the same.
 9. The semiconductor device ofclaim 1, wherein a thickness of the thinner portion is 2 to 10 nm. 10.The semiconductor device of claim 1, wherein the etch mask layer isdisposed on a top surface of the first thicker portion and a top surfaceof the second thicker portion, wherein the etch mask layer is spacedapart from the thinner portion.
 11. A semiconductor device comprising anactive region and an isolation region, wherein the semiconductor devicecomprises: a substrate; a group III-V body layer, disposed on thesubstrate; and a group III-V barrier layer, disposed on the group III-Vbody layer in the active region, wherein the group III-V barrier layercomprises a thinner portion, a first thicker portion, and a secondthicker portion in the active region, wherein the first thicker portionand the second thicker portion are respectively disposed at two sides ofthe thinner portion, the thinner portion surrounds the first thickerportion, and the second thicker portion surrounds the thinner portion.12. The semiconductor device of claim 11, further comprising an etchmask layer disposed on the first thicker portion and the second thickerportion.
 13. The semiconductor device of claim 12, wherein the etch masklayer is spaced apart from the thinner portion.
 14. The semiconductordevice of claim 12, wherein a composition of the etch mask layercomprises silicon nitride or silicon oxide.
 15. The semiconductor deviceof claim 11, further comprising a passivation layer disposed on thegroup III-V barrier layer.
 16. The semiconductor device of claim 15,wherein the passivation layer is separated from top surfaces of thefirst thicker portion and the second thicker portion.
 17. Thesemiconductor device of claim 15, further comprising a gate electrodeand at least two source/drain electrodes respectively penetrating thepassivation layer.
 18. The semiconductor device of claim 15, furthercomprising a plurality of interconnections disposed on a top surface ofthe passivation layer.
 19. The semiconductor device of claim 11, furthercomprising a passivation layer is disposed in the active region and theisolation region.
 20. The semiconductor device of claim 11, wherein athickness of the first thicker portion is 30 to 80 nm, a thickness ofthe second thicker portion is 30 to 80 nm, and a thickness of thethinner portion is 2 to 10 nm.